Automated Design of a 3GHz, 24Gbps Digital Equalizer
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چکیده
Automated design of a 4-channel, 3GHz per-channel digital equalizer using commercial ASIC design tools and a hierarchical placement Matlab code is described. Each channel is a 16-tap, 10bits per tap linear FIR equalizer. The design is in 90nm CMOS, runs with a 1.5GHz clock, and is intended for multi-tone highspeed backplane serial link applications. Design methodology and some restrictions of commercial tools are covered in detail.
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تاریخ انتشار 2006